This invention relates generally to the field of semiconductor integrated circuits. More particularly, this invention relates to a circuit and method of testing and debugging internal integrated circuit chip functions as well as testing and debugging of integrated circuit chips in their board environment.
Integrated circuit chips have increased in complexity since their inception years ago. The first chips implemented a few logic gates. Today, one integrated circuit device may consist of one hundred thousand or more gates. This level of integration is VLSI, or Very Large Scale Integration. Entire processors can be implemented on a single chip, where before hundreds of separate chips were required.
As the number of gates in an integrated circuit chip increases, the difficulty of testing the chip increases correspondingly. The method of using hand-selected input combinations can no longer easily control and observe all internal gates. Logic in known integrated circuits now consists of state machines implemented by memory elements. With the increasing complexity of integrated circuits, the parameters of test development time, maintenance time, execution time, and storage space requirements escalate, while obtainable fault coverage decreases. Recently, the cost of this method has become unacceptable.
Known graphics systems use a memory, such as a frame buffer, for storing pixel values to be displayed on a monitor. Digital logic between the frame buffer and the monitor, also called video back-end logic, interprets and manipulates the pixel values for display. Testing the digital logic between the frame buffer and the monitor in a graphics system is a difficult problem for two reasons. First, the high data rates require fast test logic and data compression. Second, the video back-end logic may contain large amounts of embedded memory, such as colormaps, which require significant time to test exhaustively.
Because of these problems, known video systems have incorporated very limited, if any, testing capability. For example, the setup screens in some known systems were designed to contain examples of all supported display modes. This allowed limited testing to be done by visual inspection of the setup screen.
Other known systems have included a degree of support for automatic testing in their video logic. However, this test support is frequently limited to production testing. Once the unit is in the field, it can no longer be automatically tested. In other cases, the test support provided is sufficiently limited that a comprehensive test of the video subsystem would take hours. In these cases, automatic self test is possible, but not very practical.
Another known system contains a register that latches the digital data prior to the digital to analog converter (DAC) that drives the monitor. The latch can capture any single pixel in the frame of pixel data by positioning the cursor to that location. Every 1/60th of a second, during vertical retrace, the processor can examine the latched pixel value. In order to test each pixel, nearly 900,000 frames must by tested, which would take 4 hours or more. Since this is impractical, only limited testing is actually performed.
While some forms of on chip testing are known, as integrated circuits increase in complexity, a dedicated test bus and logic gets increasingly expensive. The dedicated test architecture exacts a toll in chip area and reduced yield due to failures in the test architecture itself. For these reasons, a dedicated test architecture in complex integrated circuits is not attractive.
It is known to use so-called Linear Feedback Shift Registers (LFSR) in computer systems. A LFSR is a shift register with the output fed back into some of the input stages. It consists of three basic components: memory elements in the form of delay flip-flops, modulo-two summers in the form of exclusive-OR gates, and binary constant multipliers.
The LFSR performs a division operation, a property that has applications in pseudo-random number generation and signature analysis. The transition from the current state of the register to the next state is equivalent to division of the input by the register's characteristic polynomial. The register's characteristic polynomial is determined by which of the input stages has the output of the LFSR fed into them. The remainder after each division step is the state of the register.
When a LFSR is initialized with a non-zero value, and the inputs are tied to a constant, the state of the register cycles through a sequence of pseudo-random numbers. Although the numbers produced are predictable, they satisfy certain random-number properties that make the numbers useful as test input vectors. For an LFSR of thirty-two stages, over four billion unique states result.
When the register inputs are tied to a bus, the state of the register can be used as a signature. This signature is unique for a specific input string with a very high probability. This signature can be compared to an expected signature to test the validity of the tested signature. It would be desirable to incorporate a LFSR into an integrated circuit to provide chip testing at both the circuit level and at the board level.
It would also be desirable to use a LFSR as a parallel signature analyzer. Parallel signature analyzers are convenient and inexpensive to use because multiple input bits are analyzed concurrently.
It would also be desirable to use a LFSR in an integrated chip test architecture in which a common bus is used to load data into the registers of the integrated circuit and to carry test data. In this way, the expenditure of integrated circuit chip area is minimized.